Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device.
If a write command is inputted, a semiconductor memory device, for example, DRAM DDR3 operates in synchronization with a clock signal according to dynamic on-die termination (DODT). Furthermore, if an on-die termination (ODT) command is inputted, the semiconductor memory device operates in synchronization with a clock signal according to normal ODT. Furthermore, if a read command is inputted, a data output operation of the semiconductor memory device operates in synchronization with a clock signal according to CAS write latency (CWL) and read latency (RL) determined by a mode register set (MRS). Here, the RL may be expressed as the sum of additive latency (AL) and CAS latency (CL).
In particular, an ODT operation and a read operation are performed within the RL or CWL. In order that the ODT operation and the read operation are performed at a timing specified by Joint Electron Device Engineering Council (JEDEC) from when write/read/ODT commands are inputted, the semiconductor memory device may delay the corresponding commands by using the RL or CWL such that the corresponding command is in accord with an external clock signal regardless of operation frequencies or various conditions.
Korean Patent No. 625298 (hereafter, referred to as the related art) has disclosed a technology which is capable of determining an enable time of an ODT circuit by using latency information. The technology proposes a control method which compares an external clock counting signal and a delay locked loop (DLL) clock counting signal. However, this method may require a large area of a semiconductor memory device and a continuous operation by a counter. Therefore, unnecessary power consumption may occur.
Meanwhile, if data are transferred from one area to another area in the semiconductor memory system which operates in synchronization with a clock signal, an operation for synchronizing the data with the clock signal of the other area is required. Here, the operation for transferring data to the other area is referred to as a domain crossing operation. That is, the domain crossing operation is an operation for synchronizing a data output enable signal with, for example, a clock signal of a DLL.
In such a domain crossing operation, when the data output enable signal is outputted in synchronization with the clock signal of the DLL, delay may occur in a data path. Therefore, as the operation frequency of the semiconductor memory device increases, it becomes difficult to control the data output enable signal in accord with an activation time. Moreover, an area for a domain crossing block is required. For this reason, the domain crossing operation may act as a limitation in designing the semiconductor memory device.
Meanwhile, the DLL included in the semiconductor memory device generally has a closed loop type. The closed-loop-type DLL may perform several feedback operations until locking is accomplished. Therefore, much time may be required for the locking, and power consumption may increase. For reference, the locking refers to an operation for generating an internal clock signal obtained by compensating for a delay element inside the semiconductor memory device with respect to an external clock signal.